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2010-2012 Microchip Technology Inc.

DS39977F-page 11

PIC18F66K80 FAMILY

1.0

DEVICE OVERVIEW

This document contains device-specific information for

the following devices:

This family combines the traditional advantages of all

PIC18 microcontrollers – namely, high computational

performance and a rich feature set – with an extremely

competitive price point. These features make the

PIC18F66K80 family a logical choice for many

high-performance applications where price is a primary

consideration.

1.1

Core Features

1.1.1

nanoWatt TECHNOLOGY

All of the devices in the PIC18F66K80 family incorpo-

rate a range of features that can significantly reduce

power consumption during operation. Key items include:

Alternate Run Modes: By clocking the controller

from the Timer1 source or the Internal RC oscilla-

tor, power consumption during code execution

can be reduced.

Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active. In these states, power consumption can be

reduced even further.

On-the-Fly Mode Switching: The power-managed

modes are invoked by user code during operation,

allowing the user to incorporate power-saving ideas

into their application’s software design.

nanoWatt XLP: An extra low-power BOR and

low-power Watchdog timer

1.1.2

OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC18F66K80 family offer

different oscillator options, allowing users a range of

choices in developing application hardware. These

include:

External Resistor/Capacitor (RC); RA6 available

External Resistor/Capacitor with Clock Out (RCIO)

Three External Clock modes:

- External Clock (EC); RA6 available

- External Clock with Clock Out (ECIO)

- External Crystal (XT, HS, LP)

A Phase Lock Loop (PLL) frequency multiplier,

available to the external oscillator modes which

allows clock speeds of up to 64 MHz. PLL can

also be used with the internal oscillator.

An internal oscillator block that provides a 16 MHz

clock (±2% accuracy) and an INTOSC source

(approximately 31 kHz, stable over temperature

and VDD)

- Operates as HF-INTOSC or MF-INTOSC

when block is selected for 16 MHz or

500 kHz

- Frees the two oscillator pins for use as

additional general purpose I/O

The internal oscillator block provides a stable reference

source that gives the family additional features for

robust operation:

Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference

signal provided by the internal oscillator. If a clock

failure occurs, the controller is switched to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset, or wake-up from Sleep

mode, until the primary clock source is available.

1.1.3

MEMORY OPTIONS

The PIC18F66K80 family provides ample room for

application code, from 32 Kbytes to 64 Kbytes of code

space. The Flash cells for program memory are rated

to last up to 10,000 erase/write cycles. Data retention

without refresh is conservatively estimated to be

greater than 20 years.

The Flash program memory is readable and writable.

During normal operation, the PIC18F66K80 family also

provides plenty of room for dynamic application data

with up to 3.6 Kbytes of data RAM.

1.1.4

EXTENDED INSTRUCTION SET

The PIC18F66K80 family implements the optional

extension to the PIC18 instruction set, adding eight

new instructions and an Indexed Addressing mode.

Enabled as a device configuration option, the extension

has been specifically designed to optimize re-entrant

application code originally developed in high-level

languages, such as ‘C’.

PIC18F25K80

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PIC18LF46K80

PIC18F65K80

PIC18LF65K80

PIC18F66K80

PIC18LF66K80

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